Acceleration of FPGA placement
نویسنده
چکیده
Placement (and routing) of circuits is very computationally intensive. This intensity has motivated several attempts at acceleration of this process for application-specific integrated circuits (ASIC) and Field-programmable gate arrays (FPGA). In this paper an overview of some of these attempts is given. Specifically, parallelization of the standard simulated annealing (SA) algorithm is examined as well as a particular improvement to VPR, the academic Versatile Place and Route tool. Overall, it is clear that SA is difficult to parallelize and that very minor improvements on a well-known tool is cause for publication. A discussion is provided outlining a more innovative and potentially fruitful direction for acceleration of placement and routing.
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